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What the model captures

FEMU models protocol handling, selected device policies, and resource-based completion timing. Accuracy depends on the selected path and its calibration. Use the timing guide for the exact scheduling rules and policies for their execution boundaries.

Modeled mechanisms​

  • Black-box mapping, out-of-place writes, victim selection, relocation, and erase.
  • Page, DFTL translation-cost, hybrid, and FAST variants, with their documented allocation and merge behavior.
  • Optional DRAM cache membership, write coalescing, Flush, and FUA behavior.
  • Configurable NAND array times, cell/page-type tables, channel phases, and program/erase suspend on the adapters that enable them.
  • Multi-plane erase in black-box line GC; ordinary reads/programs remain separate.
  • ZNS state and resource checks, zone placement/reset, and allocated ZRWA windows.
  • FDP placement and reclaim-unit management, plus separate KV and CSD paths.
  • A CXL SSD (femu-cxl-ssd) with its own cache and media path; see the CXL SSD guide and choosing a mode.
  • Optional link bandwidth, propagation, and serialized firmware service.
  • ECC latency tiers, read-triggered refresh, and periodic error-status insertion.

Concrete boundaries​

BoundaryConsequence for an experiment
Volatile host-memory backingProcess exit/device teardown loses emulated storage; guest reset is not a supported persistence contract. power_loss=on simulates a power cut that drops buffered writes, not a persistent store
No cell voltages or raw bit-error processECC and refresh are timing/policy approximations, not physical reliability models
No general sub-page read-modify-write modelPartial-page workloads do not automatically incur a real drive's full programming cost
DFTL retains the complete host L2P tableCache-size experiments model translation costs, not an equally small host-memory implementation
Black-box LUN gate versus ZNS plane gateEqual geometry labels do not imply equal concurrency across modes
Copyback and cache-read APIs lack reviewed production callersUnit-test coverage of the API is not an enabled workload feature
CSD uses explicit or scaled host execution timeHost execution on nr_cu compute-unit threads and simplified completion-time accounting shape results
Shared controller resources across namespacesMixed-mode comparisons include shared-thread and service-time interactions
Real guest and emulator schedulingObserved completion may be later than the modeled deadline

Report the exact source commit and configuration, not just a device-mode name. For a claim about a particular SSD, supply calibration measurements and a workload that exercises the mechanism being compared. The default values alone do not establish that match.

Implementation sources​

Reviewed against FEMU 39a55eeb637b. The examples describe this revision; see validation coverage.